Hardware Systems Architect

About the role

Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems.

What you’ll do

• Own system path-finding and architecture for your domain across the breadth of compute Anthropic deploys — from concept and requirements through spec, design review, and deployment — and act as a reviewer and thought partner across the others.
• Write and own high-level requirements and specifications — system, board, interface, rack — that partners and internal teams build against.
• Review partner and vendor designs against our requirements, make the build / buy / co-design calls with supply chain and partnership teams, and surface misalignment or schedule risk early enough to act on it.
• Drive the interconnect and networking architecture that ties our systems together — scale-up and scale-out fabrics, NICs and switches, optics, and topology.
• Drive board-, chassis-, and system-level architecture with our partners — major component placement, PCB architecture, connector and cable design, and power and thermal budgeting — at the chassis, rack, and data-hall level.
• Develop performance simulations, hardware models, and "what-if" scenarios to evaluate and choose between candidate hardware architectures.
• Define validation, bring-up, and qualification strategy for new platforms — including the telemetry and reliability targets they need to hit in the fleet — and track the technology roadmaps and vendor landscape that shape what we deploy in the short and long term.
• Partner with ML performance and infrastructure software teams so hardware decisions land well for the workloads that actually run on them.
• Help shape how hardware engineering operates at Anthropic — develop and apply AI-assisted approaches to design, spec review, and validation; establish review forums, spec standards, and partner engagement.

What they’re looking for

Select a requirement to inspect fit, evidence or application context.

• Deep, hands-on expertise in at least one core hardware-systems domain (e.g., interconnect, power, thermal) for large-scale compute or networking systems.
• Experience owning hardware system architecture at scale — machine, rack, row, and cluster — and authoring specifications and requirements.
• Experience taking hardware from architecture through bring-up and high-volume production deployment.
• Experience working with external hardware vendors and partners — reviewing their designs and holding them to a specification.
• Ability to reason about trade-offs across adjacent hardware domains (e.g., interconnect ↔ power ↔ thermal ↔ mechanical) rather than within a single one.
• Track record of technical leadership — owning directional decisions and their consequences, and driving alignment across teams and partners.
• Comfort operating with high autonomy and limited process in a fast-moving, ambiguous environment.
• Strong written communication — you'll write specs and reviews that many teams depend on.
• A field relevant to the role as demonstrated through coursework, training, or professional experience

Helpful, not always essential

• 8+ years in hardware systems architecture or engineering for hyperscale, HPC, AI/ML, or high-end networking platforms.
• Experience with AI accelerator systems (GPU, TPU, or other custom ASIC platforms) and their scale-up / scale-out fabrics.
• Familiarity with the chip-package-system interface and co-design.
• Experience establishing a new function, program, or engineering practice.
• Comfort working with — and curiosity about pushing — AI tools as part of an engineering workflow.
• Degree in EE, CE, ME, CS, or a related field, or equivalent experience.
• Depth in one or more of:
• High-speed SerDes, PCIe/CXL, Ethernet/InfiniBand, and optical interconnect.
• BMC and platform firmware, hardware root of trust, and secure boot.
• 48V/HVDC power delivery and direct liquid cooling.
• Fleet-scale reliability engineering and RAS architecture.
• Signal and power integrity.